1. Field of the Invention
The present invention relates to an interface circuit that receives a strobe signal output from a semiconductor device such as a memory and LSI and a data signal synchronized with the strobe signal and adjusts the phase shift amount of the strobe signal to latch the data signal.
2. Description of Related Art
FIG. 13 shows a DDR-SDRAM (Double Data Rate Synchronous Dynamic Random-Access Memory) and its interface circuit according to a related art. As shown in FIG. 13, an interface circuit 110 is placed between a DDR-SDRAM 103 and an internal circuit 125 of a semiconductor device 102.
The interface circuit 110 includes a capture circuit 112, a variable delay circuit 113, and a delay adjustment circuit 114. The interface circuit 110 latches a data signal (DQ signal) which is output from the DDR-SDRAM 103 into the capture circuit 112 at the timing of a data strobe signal (DQS signal) which is phase-shifted by the variable delay circuit 113. The DQ signal which is latched into the capture circuit 112 is output to the internal circuit 125.
A DQS signal is phase-shifted so as to latch a DQ signal at the center of a data valid window of the DQ signal. FIG. 14 shows a DQ signal and a phase-shifted DQS signal. A DQ signal and a DQS signal are input to the interface circuit 110 in phase with each other. Thus, the shift amount of a DQS signal is normally 90-deg (shifted DQS) at which a timing margin is maximum (c.f. Japanese Unexamined Patent Application Publication No. 2006-85650, for example). Referring to FIG. 14, the shaded area of the DQ signal contains jitter, setup time, hold time and so on, and the period excluding this area is a data valid window, the midpoint (center) of which is optimum capture timing.
However, because of the phase lag between a DQ signal and a DQS signal which occurs due to a delay difference in DIMM (Dual Inline Memory Module) substrate, a delay time (tPD) difference inside a chip and so on, the 90-deg shift is not a true optimum value in many cases. A timing budget is becoming strict with the recent trend for increasing speed. For this reason, beginning with DDR2, a technique of adjusting a shift amount for optimizing the timing has been employed. A typical example of this technique is to detect a readable range while changing a delay shift amount and set a shift amount to its center (at the position where a timing margin is maximum). As shown in FIG. 15, such a technique generates a plurality of shifted DQS signals (S12 to S16) with various shift amounts of the DQS signal, detects a setup limit (X-deg shift: S12) and a hold limit (Y-deg shift: S16), and determines its middle position ((X+Y)/2 deg shift: S14) as the optimum timing (c.f. Japanese Unexamined Patent Application Publication No. 2004-185608 (Sekiguchi et al.) for example).
Referring back to FIG. 13, the interface circuit 110 includes the variable delay circuit 113 and the delay adjustment circuit 114 in order to perform such delay adjustment. The variable delay circuit 113 generates a DQS signal with a delay value=tMINDLY+tDLYSTEP*n where a minimum delay amount is tMINDLY, a step value of a variable delay is tDLYSTEP, and n is an integer of 0 or above. The capture circuit 112 captures a DQ signal with a DQS signal having each delay value, and an expectation matching circuit 141 checks whether a value matches with an expected value, thereby determining if the reading is a success or not. The delay adjustment circuit 114 thereby detects a setup limit and a hold limit. A delay amount calculation circuit 142 calculates its middle position as an optimum delay amount, and a delay setting circuit 143 sets the optimum delay amount as a delay value of the variable delay circuit 113.
However, if the speed becomes even higher and the operating frequency (data transfer speed) of DDR2 becomes 800 Mbps (DDR2-800), it is unable to detect a setup limit. It is thus unable to set an optimum value of the timing in such a case. Although slight deviation is allowable if the operating frequency is about 667 Mbps as in DDR2-667, accurate optimization is necessary for the frequency of 800 Mbps or higher, thus requiring the detection of a setup limit.
If an input DQ signal is faster than an input DQS signal due to a delay difference in DIMM substrate or the like or a limit of a minimum delay value of the variable delay circuit 113 is later than a setup time, it is unable to detect a setup limit. Specifically, a limit for advancing the phase of a DQS signal with respect to a DQ signal is generated. In such a case, a DQ signal is latched within a data valid window in spite of a minimum delay, and it is thus unable to detect a setup limit. Specifically, if the position where an input DQS signal is shifted by X-deg is a setup limit, and a minimum delay amount of the variable delay circuit 113 is the position where it is shifted by Z-deg as shown in FIG. 16, a setup limit cannot be detected. Further, even if a minimum delay amount of the variable delay circuit 113 is smaller than X-deg, it is difficult to detect a set up limit when an input DQ signal is faster than an input DQS signal due to line delay or the like.
The above problem is described hereinafter in further detail. In FIG. 13, a DQ signal which is output from a DQ terminal 131 of the DDR-SDRAM 103 is Nd101, and a DQS signal which is output from a DQS terminal 132 of the DDR-SDRAM 103 is Nq101. As shown in FIG. 17, the DQ signal Nd101 and the DQS signal Nq101 are output in phase with each other.
A DQ signal which is input to the interface circuit 110 through a DQ terminal 121 and an input/output buffer 123 of the a semiconductor device 102 is Nd103, and a DQ signal which is output from the capture circuit 112 is Nd104. ADQS signal which is input to the variable delay circuit 113 of the interface circuit 110 through a DQS terminal 122 and an input/output buffer 124 is Nq102, and a DQS signal which is phase-shifted by the variable delay circuit 113 is Nq103. As shown in FIG. 17, the DQ signal Nd103 contains jitter of tJITTER. The DQS signal Nq102 is earlier than the DQ signal Nd103 by tSKEW due to line delay or the like.
An optimum delay amount of the DQS signal Nq103 is tBSTDLY, Specifically, a rising edge of the DQS signal Nq103 is optimally at the center (t103) of a data valid window excluding a setup time tSETUP and a hold time tHOLD as shown in Nq103 (best).
If a clock cycle is tCYC, a jitter of a DQ signal is tJITTER, a setup time is tSETUP, a hold time is tHOLD, a skew between a DQ signal and a DQS signal is tSKEW, an optimum shift amount is tBSTDLY, an actually required shift amount is tACTDLY, a minimum delay amount of the variable delay circuit 113 is tMINDLY, each signal satisfies the following:
                              Maximum          ⁢                                          ⁢          pass          ⁢                                          ⁢          delay          ⁢                                          ⁢                      t            PASSMAX                          =                              t            CYC                    -                      t            JITTER                    -                      t            HOLD                    -                      t            SKEW                                                                                                      Calculated                ⁢                                                                  ⁢                delay                ⁢                                                                  ⁢                amount                ⁢                                                                  ⁢                                  t                  ACTDLY                                            =                                                (                                                            t                      MINDLY                                        +                                          t                      PASSMAX                                                        )                                /                2                                                                                        =                                                (                                                                                                                                          t                            CYC                                                    +                                                      t                            MINDLY                                                    -                                                                                                                                                                                          t                            HOLD                                                    -                                                      t                            JITTER                                                    -                                                      t                            SKEW                                                                                                                                )                                /                2                                                                                                                                Ideal                ⁢                                                                  ⁢                delay                ⁢                                                                  ⁢                amount                ⁢                                                                  ⁢                                  t                  BSTDLY                                            =                                                (                                                            t                      SETUP                                        -                                          t                      SKEW                                        +                                          t                      PASSMAX                                                        )                                /                2                                                                                        =                                                                    (                                                                                                                                                      t                              CYC                                                        -                                                          t                              JITTER                                                        +                                                                                                                                                                                                          t                              SETUP                                                        -                                                          t                              HOLD                                                                                                                                            )                                    /                  2                                ⁢                                  t                  SKEW                                                                                                                                                Error                ⁢                                                                  ⁢                amount                ⁢                                                                  ⁢                                  t                  ERROR                                            =                                                t                  ACTDLY                                -                                  t                  BSTDLY                                                                                                        =                                                (                                                            t                      MINDLY                                        -                                          t                      SETUP                                        +                                          t                      SKEW                                                        )                                /                2                                                        wheretBSTMR=(tCYC−tJITTER−tSETUP−tHOLD)/2tBSTMR>>tERROR when tCYC>>tMINDLY, tJITTER, tHOLD, tSKEW 
If the speed becomes higher, the minimum delay amount tMINDLY becomes larger than the setup time tSETUP and its position t102 is later than a setup limit t101, resulting in a failure to detect the setup limit t101. Therefore, an optimum delay amount which can be obtained in the delay adjustment circuit 114 is tACTDLY. Thus, the DQS signal Nq103 is shifted to the center (t104) excluding the minimum delay amount tMINDLY and the holding time tHOLD, which is deviated from the original optimum delay position (t103) by tERROR. If the operating frequency is about 667 Mbps, the clock cycle tCYC is sufficiently larger than tMINDLY, tJITTER, tHOLD, tSKEW, tBSTMR and therefore tBSTMR is sufficiently larger than tERROR as described earlier, so that the lag tERROR does not cause any significant problem.
However, the operating frequency is 800 Mbps in DDR2-800, and the proportion of tMINDLY, tJITTER, tHOLD, tSKEW and tBSTMR is significantly large with respect to the clock cycle tCYC as shown in FIG. 18. In this case, a data valid window between a setup limit t111 and a hold limit t115 is narrowed and a minimum delay position t112 is significantly later than the setup limit t111, so that the proportion of the lag tERROR between the original optimum delay position t113 and an actual calculated delay position t114 with respect to tBSTMR is large. An increase in the proportion of tERROR means an increase in the probability of a failure in reading of a DQ signal. It is therefore necessary to eliminate tERROR and capture a DQ signal at the center of a data valid window.